Computer Busses


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Types of Buses in Computer Architecture

In fact, the entire diagram might be considered to be a description of the control bus - and only the control bus.


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It is an excellent visual on what certain sub systems do and even what directly controls certain resources, but there is absolutely no indication of what's actually being hard wired or how an entire computer really works at least in terms of bus structure. Sign up to join this community. The best answers are voted up and rise to the top. Home Questions Tags Users Unanswered. Trying to understand a picture of computer buses Ask Question. Asked 7 years, 1 month ago. Active 7 years, 1 month ago.

Viewed 3k times. It is not named in the picture, and what is its name? How is the data flow like?

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For example, are my following understanding correct? How are data flows between non-CPU components like? Tim Tim 1. A bus is just a medium of communication with the following properties: Multiple entities can be connected to it If one entity sends a message or "does something" to the bus, every other entity can see it Bad things will happen if two entities try to communicate at the same exact time A protocol or set of rules is needed so that all components on the bus have a system where they can take turns using it.

Usually this protocol is different according to the purpose and speed of the bus Some sort of addressing scheme is used where devices can say who they are and who they want to talk to Bad things will happen if multiple entities have the same address At the very least entites wanting to "talk" on the bus need to look to see if there is activity going on before they try to send data through it Entities wanting to "listen" on the bus generally need to listen for their own address and only snatch the data meaningful to them If you have any knowledge of networking and most of this sounds familiar it's pretty much similar in concept.

To answer your questions: Looks to me like the CPU needs to go through the processor bus, northbridge and PCI bus to get to southbridge. I believe they represent connects to the busses.

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To me it looks like the labels are identifying the thicker light blue lines. The diagram could be a bit better IMHO.

Bus architecture and how register transfers work - 8 bit register - Part 1

Note that AGP stands for "Accelerated Graphics Port " - technically it's not a bus as multiple components don't come into play there one of the whole reasons AGP was invented. To software it appears as another PCI bus, though. I think so. See my initial paragraph. It's possible for a bus to be connected to another bus and take on responsibility of forwarding data through it. LawrenceC LawrenceC Anono Anono 21 1 1 bronze badge. No, this "bus" doesn't exist as described.

But in the scenario of a communication to the devices in the lower-half of the diagram, data must pass through the "bus" from the CPU to the northbridge I quote bus because the NB may be integrated on the CPU , and then again over what typically is a PCI bus to the SB, and vice versa for the round trip.

There's no one straightforward way to answer this question as processors today are becoming more complex and thus taking different approaches to memory, bus, and cache access.

(PDF) Computer Busses, Ports and Peripheral Devices | Nikola Zlatanov - mistrapalve.tk

Most modern processors have integrated memory controllers, thus there is no need to talk to the northbridge for DMA. Encrypted messages can be transmitted to or out of any of the connected device attached to the external data bus. Think of the data bus like a giant highway with parallel lanes. On that analogy, bits are the cars traveling side by side-each other carrying part of a coded message.

The data as defined earlier carries data within the computer system, while the address bus determines where the data should be transmitted to. So, in this, we light I define address bus as a computer bus structure used to transmit data between devices that are described by the hardware address of the physical memory, which is put in the form of binary numbers i. The central processing unit does the writing and also the reading of all the address busses in the form of bits.

Address bus was built into the computer motherboard to make computer compatible, less costly and to allow many more devices to be able to connect to the computer. The address bus is assessed by the quantity of memory a system is capable of regaining. A system with a bit address bus can address mebibytes equivalent to 4 gibibytes of memory space. Computers with bit address bus with a condition of having an operating system that can support the address bus will be able to address 16, pebibytes the equivalent of 16 exbibytes of memory locations, which is considered extremely large.

Bus organization of 8085 microprocessor

It is the primary characteristic of a nondirectional attribute. An example of which include Intel microprocessor, which has 16 bits Address bus. The implication of this is that this microprocessor Intel can transmit up to 16 bits address i. This bus combines several signals into a single signal of 8 bits data bus. Therefore, the most notable bits of address passes through an Address bus A7-A0.

Remember we talked of three main type of computer bus which are; data bus, address bus and now this is control bus. After the data bus and the location sends the data is known by the address bus then control bus is needed for the proper execution of the data. The control bus is then a particular kind of computer bus that the central processor uses to communicate other components and devices connected to the computer system.

The control bus is most important in the sense that the control of all connected devices. And also computer system components with the help of varieties of a control signal transmitted by the central processing unit is made possible by this control bus. Not forgetting one of the primary objectives of a bus is to minimize where possible the lines that are needful for communication in a computer system.

On the contrary to an individual bus which allows the communication between devices using one data line i. And its devices and also helps the central processing unit coordinate and unify the control signals in internal devices and external components. Interrupt Request IRQ Lines: It is a specified type of hardware line used by devices to interrupt the current stream of data to enrooted to the central processing unit.


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  • It allows the computer to do so many tasks simultaneously by interrupting an ongoing process to get a task quickly done due to its high priority. Most system buses comprise of 50 to discrete lines for communication. Communication between computer central processing unit and control bus is of great importance so that the computer system can function properly and proficiently. The central processing unit cannot know for sure if the system is sending or receiving data without the control bus. Where the write and read information have to go is managed and regulated by the control bus. A signal is transmitted to the write command line immediately the central processing unit writes a data or command that is addressed to the central computer memory, and a signal is also sent by the central processing unit when it needs read from the system memory.

    This signal permits the CPU to receive or transmit data from the main memory. Microprocessor process data with the help of the control bus that is what to do with the selected memory location. Some control signals include Read, Write and Opcode fetch. Highlight here that a microprocessor performs various kinds of operations with the help of this same control bus. The control bus is dedicated for all timing signals are managed according to the control signal from the control bus. The present disclosure generally relates to electronic communications.

    More specifically, the present disclosure relates to systems and methods of DBI encoding based on the speed of operation. Data Bus Inversion DBI is applied when the aim is to raise power integrity and signal and simultaneously reduce power consumption. We can not overemphasize the use of data bus inversion when we have to transfer a large quantity of data with the maximum speed ever possible. The simple bus systems had a critical setback when used for general-purpose computers.

    The entire devices placed directly on the bus had to operate at the same speed dictated by the bus. As they all shared a single clock system. It became a hard task when increasing the speed of the central processing unit is the aim. Because to achieve this, the speed of all the devices on the bus just as well be increased. So, the CPU has to wait or work at a very ridiculous slower clock frequency to communicate with other devices in the computer system.

    While acceptable in embedded systems, this problem was not for long tolerated in general-purpose and also in user-expandable computers.

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